As a communication scheme of mobile broadband communication, there is a TDD (Time Domain Duplexing) scheme that switches uplink and downlink communication to high speeds using the same frequency band in the uplink and downlink communication. For example, a switching time of transmission/reception of a base station is prescribed in LTE (Long Term Evolution) that is a high-speed communication standard. According to this prescription, the base station needs to shorten a switching time of transmission/reception to not more than 17 μs (Non Patent Literature 1).
In addition, in a communication device of the TDD scheme, it is necessary to suppress noise that sneaks in a reception system from a transmission system during a reception period in order to improve reception sensitivity of the reception system. Therefore, control may be performed to cut off power source supply to an amplifier of the transmission system during the reception period. In addition, since an envelope of a signal has a broadband frequency component particularly in a communication device that deals with a complex multi-level digital modulation wave among communication devices of LTE, a voltage needs to be stabilized so that a bias circuit, such as the amplifier, does not fluctuate. Therefore, it is general that decoupling of the bias circuit is performed in a broadband (it may be generally called a video band in many cases) ranging from a DC band to several 100 MHz bands. For example, in the amplifier of the transmission system of the base station, a decoupling capacitor having a μF-class capacitance (approximately 0.1 to 50 μF) is connected in the vicinity of an amplifying transistor and the bias circuit for the purpose of decoupling. Note that the amplifying transistor includes an FET (Field Effect Transistor) etc. Accordingly, in a case of controlling power source supply to the amplifying transistor of the amplifier of the transmission system, charge and discharge to the decoupling capacitor is needed. For example, in a case of providing the decoupling capacitor near a gate terminal of the amplifying transistor, it may be considered to connect a discharging resistor in parallel with the decoupling capacitor. However, since the discharging resistor has a resistance value of approximately several kΩ, charges of the decoupling capacitor cannot be discharged at high speed only by the discharging resistor, in a case of turning off a gate voltage to the amplifying transistor. For this reason, a charge and discharge time to the decoupling capacitor may be long and, for example, may be a time of μs or more in some cases. Therefore, it is difficult in many cases to use the transistor in the vicinity of which the decoupling capacitor is connected for applications requiring high-speed ON/OFF of the transistor.
Patent Literature 1 is an example of a technology for realizing high-speed ON/OFF of the transistor. Patent Literature 1 discloses a configuration in which a circuit is formed by a capacitor (0.1 μF in an example in the specification of Patent Literature 1) provided close to a gate terminal of an amplifying transistor, and a discharging resistor provided in parallel with the capacitor, the circuit having a time constant at the time of discharge, and having a switch element in order to discharge charges of the capacitor at high speed. In Patent Literature 1, charge and discharge to the capacitor provided close to the gate terminal of the amplifying transistor is performed by charges that pass through the switch element, the capacitor having a comparatively large capacitance, and thereby ON/OFF of the amplifying transistor is switched. Therefore, it is possible to achieve more shortening of a switching time of ON/OFF of the amplifying transistor than the time constant of discharge by the discharging resistor. However, since essentially, a configuration is employed in which charge and discharge of the capacitor having large capacitance are performed, there is a problem that it is difficult to achieve further shortening of the switching time.
Patent Literature 2 is an example of a technology controlling a gate bias of a transistor by a switch. Patent Literature 2 discloses a variable gain amplifier in which a source-grounded type amplifier and a gate-grounded type amplifier are cascode-connected. In the variable gain amplifier of Patent Literature 2, in order to make gains of all the amplifiers variable, gate biases of the plurality of source-grounded type amplifiers provided in an initial stage are selectively turned on and off, and thereby an operating point of the gate-grounded type amplifier provided in a subsequent stage is changed. In addition, Patent Literature 2 describes one example of a configuration of switches to selectively turn on and off the gate biases of the plurality of source-grounded amplifiers of the initial stage and the plurality of gate-grounded type amplifiers provided in the subsequent stage, and a technology to suppress an output impedance and load fluctuations while selectively varying gains, the output impedance and the load fluctuations being caused at the time of selectively varying the gains. However, Patent Literature 2 neither specifically describes nor suggests a configuration for switching of the gate biases at high speed.
Patent Literature 3 discloses a technology in which, in a bias circuit of an amplifying transistor, by parallel operation of a switch circuit, a supply current capability and a discharge current capability per unit time are expanded, and a switching time of ON/OFF of the amplifying transistor is reduced. However, in Patent Literature 3, there is a problem that in a case where the number of switch circuits is n, a circuit scale becomes n times larger, although the switching time can be shortened almost to a 1/n time.